In recent years, as system Large Scale Integrations (LSIs) have been complicated and speeding up, operation frequency and power consumption of Dynamic Random Access Memories (DRAMs) have been increased. Therefore, a ratio of power consumption of a DRAM to power consumption of a system is increased, which results in a problem of preventing power saving for the DRAM.
For power saving of DRAM, Patent Literature 1 discloses a technique (hereinafter, referred to as “conventional technique A”) of changing address mapping from a logical address to a physical address according to an operation mode to set a physical memory region to which no access occur, thereby stopping the physical memory region.
On the other hand, Patent Literature 2 discloses a technique (hereinafter, referred to as “conventional technique B”) of performing address mapping to selectively perform, based on a logical address to be accessed, a method of accessing the same bank or a method of accessing by bank interleaving. In conventional technique B, when the method of accessing the same bank is used, it is possible to reduce power consumption.